Formal Verification Engineer

Job Title: Formal Verification Engineer

Location: 7171 Southwest Parkway, Austin, TX 78735

Duration: 12+ Months

Employment Type: C2C

Pay Rate: $75-$80/Hour C2C

Job Description

We are looking for a skilled Formal Verification Engineer to lead design verification activities using formal verification tools and specification analysis. The ideal candidate must have hands-on experience with VC Formal or JasperGold, SystemVerilog Assertions (SVA), and Formal Property Verification (FPV) applications.

Primary Skills

• VC Formal or JasperGold
• SystemVerilog Assertions (SVA)
• Formal Property Verification (FPV)
• Design Specification Analysis

Secondary Skills

• Verilog / SystemVerilog
• RTL Design Verification
• ASIC / Semiconductor Verification
• Digital Logic Design
• Debugging and Root Cause Analysis

Key Responsibilities

• Lead design verification using formal verification tools.
• Analyze design specifications and requirements.
• Develop and validate SystemVerilog Assertions.
• Apply FPV techniques to verify hardware design functionality.
• Analyze verification results and debug design issues.
• Collaborate with design and verification teams.