Design Verification Engineer

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APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Ensure high quality silicon for IC chips and IPs. Review specifications and craft verification plans.

Execute verification according to plan to support tape out. Verify IP related to power management, such as mixed-signal circuits, LDOs, data converters, references, input-output circuits, clock circuits, etc. Verify mixed-signal IC designs using a combination of analog circuits, Verilog-AMS module and Verilog RTL in simulations.

Execute verification plans from beginning to end, including testing bench and environment bring-up, regressions, failure debug. Develop verification methodology suitable for the IP, ensuring scalability and portability. Develop verification environment, including stimuli, checkers, assertions, trackers, and coverage.

40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role.

The base pay range for this role is between $187,408 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS

• Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs.
• Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan.

You’ll also receive benefits including

• Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition.
• Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.
• Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.

Note

Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Master’s degree or foreign equivalent in Electrical Engineering, Electronics and Communication Engineering, Computer Engineering, or a related field and 2 years of experience in the job offered or related occupation.

Education and/or Experience must include

• Utilizing Hardware description languages including Verilog, SystemVerilog or Verilog-AMS to understand the issues inside digital design and models.
• Designing and developing a verification plan by utilizing analog design, verification, and debugging to identify design issues and verify analog IPs before going into production Understanding mixed-signal design, developing a verification plan and executing it, and debugging to identify design issues and verifying the complex mixed-signal IPs before going into production Writing test patterns and plans with EDA tools such as Cadence and Synopsys.
• Running mixed-signal simulations and debugging issues, utilizing Cadence or Synopsys AMS simulation tools, to identify functional issues in the IPs defined by specification documents Utilizing verification methodologies and tools, including simulators, waveform viewers, or execution automation, to guarantee complete coverage for verification.
• Running simulation and using viewers to observe outputs using Cadence or Synopsys.
• Evaluating and benchmarking the performance of Cadence analog and mixed-signal simulators, analyzing accuracy to identify simulator strengths and limitations across a range of analog and mixed-signal design.
• Debugging and resolving simulator issues in Cadence analog and mixed-signal simulation environments, distinguishing between tool-level defects and design-level issues to drive root-cause analysis and ensure simulation integrity across analog and mixed-signal IPs.
• Reproducing and triaging issues reported by tool users by re-creating simulation scenarios and design configurations, performing root-cause analysis, and driving resolution with R&D teams to ensure timely fixes.
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