SoC Design Implementation Engineer (Up to Principal Level)

Company:

Qualcomm Vietnam Company Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

The SoC

Design organization is seeking engineers to contribute to the implementation and front-end readiness of complex SoC, subsystem, and IP designs. This role focuses on design constraints, synthesis, timing analysis, power-intent implementation, and implementation collateral required to deliver high-quality netlists to downstream Physical Design, Design Verification, DFT, emulation, and signoff teams.

The successful candidate will work closely with RTL Design, SoC Architecture, Design Verification, Physical Design, DFT, CAD/methodology, power-management, and program teams across the global engineering organization.

The role requires a strong understanding of the transformation from RTL to synthesized netlist, including constraint development, synthesis optimization, timing and QoR analysis, low-power implementation using UPF, and resolution of design issues across RTL, constraints, libraries, tools, and flow configuration.

I.

Responsibilities

Design Implementation and Front-End Readiness

• Support implementation of complex SoC, subsystem, and IP designs from RTL through synthesis and handoff to downstream implementation teams.
• Review RTL hierarchy, design partitioning, clock and reset architecture, interface definitions, and implementation requirements.
• Prepare and maintain synthesis scripts, design configuration, file lists, libraries, operating conditions, scenarios, and implementation collateral.
• Coordinate design releases, dependencies, configuration updates, and implementation readiness across RTL, DV, DFT, PD, CAD, and architecture teams.
• Analyze design quality and identify RTL, constraint, library, or flow issues affecting timing, power, area, reliability, or implementation convergence.
• Support design reviews, implementation reviews, signoff reviews, and technical documentation activities.
• Investigate failures across RTL, synthesis, constraints, UPF, libraries, tool setup, and build environments; identify root cause and drive corrective action.

Constraint Development and Timing Readiness

• Develop, review, and maintain timing constraints for block, subsystem, and SoC-level designs.
• Create and validate clocks, generated clocks, clock relationships, clock uncertainty, input/output delays, loads, drive models, and operating scenarios.
• Define and review timing exceptions, including false paths, multicycle paths, asynchronous paths, clock groups, and case analysis.
• Support multi-mode, multi-corner timing analysis and ensure constraints are complete, consistent, and aligned with design intent.
• Analyze timing reports, path groups, startpoints, endpoints, slack, path exceptions, clock latency, skew, and constraint coverage.
• Debug unconstrained paths, invalid constraints, conflicting exceptions, missing clocks, generated-clock issues, and constraint-propagation problems.
• Collaborate with RTL and Physical Design teams to resolve critical paths, high-fanout issues, excessive buffering, logic depth, congestion risks, and timing-convergence challenges.
• Review constraints for synthesis, formal equivalence, DFT, static timing analysis, and physical implementation consistency.
• Develop constraint-quality checks and automation to improve constraint completeness, consistency, and reuse across projects.

Synthesis and Netlist Generation

• Run and debug RTL synthesis for blocks, subsystems, and SoC-level designs using industry-standard synthesis flows.
• Generate and review synthesis netlists, reports, databases, timing views, and implementation handoff collateral.
• Analyze synthesis results for timing, area, power, high-fanout nets, unmapped logic, inferred structures, unconnected signals, and optimization quality.
• Tune synthesis options, compile strategies, effort levels, retiming or optimization settings, and flow configuration to improve QoR while preserving design intent.
• Identify and resolve issues involving black boxes, missing or mismatched libraries, unresolved references, unintended latches, X-propagation, multiple drivers, and synthesis warnings.
• Support synthesis quality-of-results tracking and compare changes across RTL, constraints, libraries, tool versions, and implementation configurations.
• Deliver clean, traceable, and reproducible netlists for Physical Design, DFT, formal equivalence, emulation, gate-level simulation, and signoff activities.
• Partner with RTL designers to recommend RTL changes that improve timing, area, power, synthesis quality, and downstream implementation convergence.

Experience with UPF and low-power implementation is a plus

• Develop, integrate, review, and maintain UPF-based power intent for blocks, subsystems, and SoC designs.
• Define and validate power domains, supply networks, supply sets, power states, isolation strategies, level-shifter strategies, retention requirements, and related low-power structures.
• Ensure UPF intent is consistent with RTL hierarchy, power architecture, voltage domains, clock/reset behavior, and implementation requirements.
• Run and debug power-intent checks, including missing or conflicting supplies, invalid domain crossings, incorrect isolation placement, level-shifter issues, retention mismatches, and incomplete power-state definitions.
• Analyze synthesis results involving isolation cells, level shifters, retention cells, always-on logic, power switches, and other low-power implementation elements.
• Collaborate with architecture, RTL, PD, DFT, verification, and power-management teams to resolve power-intent interpretation and implementation issues.
• Support low-power equivalence, power-aware simulation, implementation handoff, and signoff readiness.
• Improve UPF methodology, reusable templates, validation checks, and automation across projects.

Quality, Debug, and Cross-Functional Collaboration

• Drive implementation quality closure across lint, CDC/RDC, connectivity, synthesis, constraints, UPF, formal, and release-readiness checks.
• Debug tool failures and design-quality issues using logs, reports, databases, waveforms, and automated analysis.
• Work with CAD and methodology teams to improve flow robustness, runtime, capacity, repeatability, and ease of adoption.
• Document implementation assumptions, constraints, exceptions, known issues, methodology decisions, and handoff requirements.
• Mentor engineers and share best practices in synthesis, timing constraints, UPF, debug, automation, and implementation methodology.

II. Level Expectations

Engineer

• Execute assigned implementation, constraint, synthesis, and UPF tasks with guidance from senior engineers.
• Analyze basic timing, synthesis, and power-intent reports and assist with issue triage and closure.
• Maintain scripts, configuration, reports, and implementation collateral according to established methodology.
• Collaborate effectively with partner teams and escalate issues with clear technical information.

Senior Engineer

• Independently own implementation activities for blocks or subsystems from setup through synthesis and handoff.
• Develop and validate timing constraints, synthesis flows, and UPF implementation for assigned design areas.
• Drive root-cause analysis and closure of timing, QoR, power-intent, and flow issues across multiple teams.
• Contribute to methodology improvements, automation, technical reviews, and mentoring.

Staff /Senior Staff Engineer

• Lead implementation of major subsystems or complex SoC design areas, including constraints, synthesis, and low-power intent.
• Define technical plans, implementation strategy, quality criteria, and handoff requirements.
• Resolve complex cross-functional issues involving RTL, architecture, tools, libraries, timing, power, and physical implementation.
• Drive reusable methodology, automation, QoR improvement, and technical alignment