Research Intern — Neural Network Training and Hardware–Software Co-Design

We're looking for an intern to design and train neural networks that run efficiently on custom hardware for wearable and robotics devices. You'll co-design models and systems that run them under tight accuracy, latency, power, and memory budgets, and own the work end to end, from training through validation on real hardware, including FPGA prototypes.

Responsibilities

• Design, train, and evaluate neural networks for on-device workloads under compute, memory, and energy constraints
• Develop hardware-aware training and model compression techniques and measure their impact on target hardware
• Explore partitioning models across multiple accelerators or chips, including how inter-chip communication affects accuracy and performance
• Profile models end to end and use the measurements to drive both model and hardware design decisions
• Prototype and validate on FPGA platforms, modifying and debugging existing RTL as needed
• Present results through a working demo and a technical write-up

Qualifications

• Currently pursuing a PhD in Computer Science, Electrical/Computer Engineering, Machine Learning, or a related field
• Hands-on experience training deep neural networks in PyTorch or TensorFlow, from data pipeline through debugging and evaluation
• Working knowledge of computer architecture: how memory hierarchy, data movement, and numerical precision affect neural network performance
• Must obtain work authorization in country of employment at the time of hire, and maintain ongoing work authorization during employment
• Intent to return to full-time degree program after completion of the internship RTL design in Verilog or SystemVerilog, including simulation and testbenches
• FPGA experience: synthesis, timing closure, and on-board bring-up and debug
• Quantization-aware training, mixed precision, pruning, or knowledge distillation
• Experience with neural network accelerators, model parallelism, or distributed inference
• C/C++ and model deployment on embedded or edge platforms
• Publications or substantial projects in efficient ML, ML systems, or computer architecture (e.g., MLSys, NeurIPS, ICLR, ISCA, MICRO, DAC)