ASIC Engineer Intern, Design Verification

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ASIC Engineer Intern,]]

Design Verification

ASIC Engineer Intern,

Design Verification

Bangalore, India

Hardware

+ 2 more

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Meta is seeking an ASIC Engineer Intern to join our Infrastructure organization. Our servers and data centers are the foundation upon which our rapidly scaling infrastructure efficiently operates and upon which our services are delivered. By holding this role, you will be an integral member of an ASIC team to build accelerators for some of our top workloads enabling our data centers to scale efficiently.

You will have an opportunity to participate in design and verification of advanced IPs using state of the art tools. Come work and learn alongside our ASIC engineers to build “Green” data center accelerators.

Internships are twelve (12) to sixteen (16) weeks long.

ASIC Engineer Intern,

Design Verification Responsibilities

• Develop tests, checkers and coverage to help verify designs.
• Develop understanding of the architecture and microarchitecture of designs.
• SystemVerilog/UVM/C code to generate test content.
• Develop scripts to automate various processes.
• Debug test failures, work with design, verification and modeling teams to fix and verify the fixes.
• Help improve verification processes and contribute to methodology.

Minimum Qualifications

• Currently has, or is in the process of obtaining, a Bachelor's degree in Electrical Engineering, Computer Engineering or related engineering fields
• Knowledge of Computer Architecture and Logic Design fundamentals
• Experience thinking critically and creatively on how to verify designs, solve problems
• Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment
• Intent to return to degree-program after the completion of the internship

Preferred Qualifications

• Currently has, or is in the process of obtaining, a Masters or PhD degree in Electrical Engineering, Computer Engineering or related engineering fields
• Knowledge of SystemVerilog/VHDL/Verilog/UVM
• Scripting with Python or perl

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You may view our Equal Employment Opportunity notice here .

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Equal Employment Opportunity Meta is proud to be an Equal Employment Opportunity employer.

We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics.

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Meta is committed to providing reasonable support (called accommodations) in our recruiting processes for candidates with disabilities, long term conditions, mental health conditions or sincerely held religious beliefs, or who are neurodivergent or require pregnancy-related support. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form

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