Senior Silicon Physical Design Engineer

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of experience with System on a Chip (SoC) cycles.
• Experience with advanced design, including clock/voltage domain crossing, DFT, and low power designs.
• Experience in high-performance, high-frequency, and low-power designs.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with scripting languages such as Perl, Python, or Tcl.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.

From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements.
• Collaborate with cross-functional teams to debug failures or performance shortfalls and meet program goals in lab or simulation.
• Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route, and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
• Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.