ASIC Verification Technical Leader || Verilog, System Verilog, Testbench, UVM || Exp - 10+ years

We are recruiting a ASIC Verification Technical Leader to architect and manage the full lifecycle verification of advanced ASICs for Cisco’s core networking platforms. Lead dynamic collaboration with verification teams, ensuring robust design and integration. Ideal for experienced ASIC design and verification professionals with strong expertise in UVM/System Verilog and related tools.