Silicon Validation Software Engineer: CPU and Memory Hierarchy

Would you like to work on SW that runs on every Apple phone, pad, and Mac computer in the world? Join our team of experienced SW engineers and debuggers in validating Apple's world class silicon. In this highly visible role you will be writing functional validation SW for the CPUs, caches, and memory subsystem of our SoCs, with the aim of identifying logic design and circuit bugs.

You will be a SW developer for a system validation tool used widely across Apple's Silicon Engineering group, and will collaborate with SoC design and product engineering teams to debug and drive silicon issues to root-cause.

Work with designers and architects to understand the functionality of various blocks in the SoC Create validation test plans, ensuring all key features are covered Develop SW workloads to validate various CPU and memory subsystem features - Integration of these workloads into an existing system validation tool Make enhancements to the tool's SW framework to support new CPU architectures Drive the bring-up and execution of our validation SW in pre-silicon (FPGAs) and post-silicon (development boards) Debug workload failures using a variety of tools and hooks Release and distribute our system validation SW to cross-functional teams across Apple

Experienced C and assembly programmer.

Experience with scripting languages such as Python, Perl, or Tcl Knowledge of software tool chains including including compilers, assemblers, and source control tools Experience with GenAI tools (like Claude code) Ability to work well in a team, but to be responsible and self-driven Strong understanding of micro-processor architecture - a plus Good knowledge of ARM or another CPU instruction set architecture - a plus Familiarity with memory technologies and power management - a plus Background in silicon bring-up and debug experience - a plus

A minimum of a BS degree and a minimum of 3 years of relevant industry experience in silicon validation software engineering or related field.