Technical Lead, Power Analysis and Optimization
Spotted 5d agoFull time
Job description
About this role
Employer-provided description, formatted for easier reading.
We are recruiting a Technical Lead, Front-End Power Optimization to oversee fullchip SDCs and collaborate with design teams to refine timing constraints for next-generation networking chips. The role requires strong ASIC design expertise and experience with SDC/STA tools, ideal for candidates with significant ASIC or related experience.
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