LandOfferLead ASIC Design Engineer
About this role
Employer-provided description, formatted for easier reading.
Locations
Austin, Texas
San Jose, California
About the Role
A fast-moving startup with offices in Austin and the Bay Area is looking for a lead RTL designer to work on their next tapeout of high-performance, low power edge-AI chips. This is a hands on technical role in which you'll own design, set technical direction and contribute to leading and managing your own teams.
Offering high ownership from day one and the opportunity to work with a world-class team of industry leaders from the top semiconductor companies, this is an exciting role for someone who wants to be a part of something from an early stage that already has a track record of first tapeout suceess.
Key Responsibilities
- Own
RTL design and microarchitecture
.
- Work on cache-coherent and non-coherent interconnects and associated protocols.
- Define and review microarchitectural specifications and translate them into robust, synthesizable RTL.
- Work closely with verification engineers on design validation, debugging and performance analysis.
- Collaborate with architecture, verification, software and system teams throughout the silicon development cycle.
What We're Looking For
- 10+ years of ASIC/SoC design experience
, with substantial hands-on RTL development.
- Strong
Verilog/SystemVerilog RTL design
experience.
- Familiarity with technologies such as
PCIe, CXL or UCIe
.
- Experience working on GPUs, AI accelerators, CPUs, TPUs is highly desirable.
- Experience with HBM, memory controllers or coherent fabrics is a strong plus.